1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a vision chip having a plurality of photo detectors (PD's) and processing elements (PE's).
2. Description of the Related Art
A variety of image processors dedicated to image processing tasks have been researched, developed, and proposed, and many of these processors incorporate a mechanism for performing some kind of parallel computation. For example, in a massively parallel processor whose degree of parallelism amounts to tens of thousands, and in which one PE (processing element) is assigned to each pixel or each group of a small number of pixels, certain kinds of image processing tasks can be performed efficiently by performing SIMD (Single Instruction Stream Multi Data Stream) type control in which the same instruction is executed simultaneously on the plurality of PE's.
Previously, such an image processor has almost always been built from a large-scale computer of a super computer class, but in recent years, with advances in semiconductor integration technology, and with growing need to handle image processing with more ease, work has been proceeding to implement such a processor on a single chip. Further, research on a device called a vision chip, on which not only processors but also PD's (photo detectors) are accommodated, has been attracting attention.
In prior known vision chips and image processing SIMD processors (semiconductor integrated circuit devices), there has been a tradeoff between the performance of each PE and the number of pixels, and it has been difficult to achieve a semiconductor integrated circuit having high versatility. Furthermore, as the structure is unfit for global computations, the device has not been able to efficiently perform processing for extracting scalar quantities from a two-dimensional pattern.
More specifically, as the ALU used in each PE in prior known vision chips is one that simply performs computations based only on data within the PE or takes outputs of neighboring PE's as its inputs, the computation capability that can be implemented is limited to local computations in which computations are performed based on data from the PE itself and its neighboring PE's. If global computations are to be implemented without disrupting the orderly arrayed structure of the vision chip, additional circuitry such as adders will become necessary, resulting in increased amount of circuitry. This runs counter to the need to reduce the amount of circuitry as much as possible for a vision chip which requires accommodating as many pixels as possible, in a limited chip area.
Furthermore, in prior known vision chips, the range of processing that can be achieved has been limited because the computation capability of each PE and the capacity of memory mounted are finite. There is a dilemma here in that if the computation capability and the capacity of memory mounted are increased in order to increase the versatility of the vision chip, then the chip area will increase.
There is thus a need to provide a semi-conductor integrated circuit device that achieves high versatility without entailing a reduction in the number of pixels (the number of PE's that can be accommodated).
The prior art and its associated problems will be described later with reference to accompanying drawings.